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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5434
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:41:58Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:41:58Z-
dc.date.issued2012-
dc.identifier.citationGhosh, D., Parihar, M. S., Armstrong, G. A., & Kranti, A. (2012). Low power nanoscale RF/analog MOSFETs. Paper presented at the Proceedings of the IEEE Conference on Nanotechnology, doi:10.1109/NANO.2012.6321973en_US
dc.identifier.isbn9781467321983-
dc.identifier.issn1944-9399-
dc.identifier.otherEID(2-s2.0-84869166884)-
dc.identifier.urihttps://doi.org/10.1109/NANO.2012.6321973-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5434-
dc.description.abstractThe present work reports on the substantial benefits of underlap Source/Drain (S/D) design in moderately inverted nanoscale MOSFETs to significantly enhance key analog/RF performance metrics. It is demonstrated that underlap S/D design alleviates the inherent trade-offs between bandwidth, gain and linearity for low power RF CMOS nanodevices. Optimal underlap region parameters are identified and design trade-offs examined. The results are significant for RFICs with nanoscale MOSFETs in emerging technologies. © 2012 IEEE.en_US
dc.language.isoenen_US
dc.sourceProceedings of the IEEE Conference on Nanotechnologyen_US
dc.subjectAnalog/RFen_US
dc.subjectDesign tradeoffen_US
dc.subjectDouble gate MOSFETen_US
dc.subjectEmerging technologiesen_US
dc.subjectLinearityen_US
dc.subjectLow Poweren_US
dc.subjectLow power RFen_US
dc.subjectMOSFETsen_US
dc.subjectNano scaleen_US
dc.subjectNano-devicesen_US
dc.subjectNanoscale MOSFETsen_US
dc.subjectPerformance metricsen_US
dc.subjectCommerceen_US
dc.subjectMOSFET devicesen_US
dc.subjectNanotechnologyen_US
dc.titleLow power nanoscale RF/analog MOSFETsen_US
dc.typeConference Paperen_US
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