A metal–ferroelectric–insulator–semiconductor transistor perspective: Nanowire or planar architecture?

Abstract

The incorporation of ferroelectric layer in a standard metal–oxide–semiconductor (MOS) structure has shown significant potential to favourably alter the charge distribution through the negative capacitance (NC) phenomenon. Since the transistor architecture has evolved from traditional planar to cylindrical nanowire, the geometrical considerations associated with the ferroelectric capacitance (Cfe), MOS capacitance (CMOS), and oxide capacitance (Cox) have become crucial to sustain the internal amplification. The architecture-dependent analytical investigation of a metal–ferroelectric–insulator–semiconductor (MFIS) transistor reflects on the requirement of a thicker ferroelectric layer to preserve the internal amplification and steep current transition in a cylindrical nanowire device as compared to a planar transistor. Based on the evaluation of device and ferroelectric parameters of four different materials (Y-HfO2, Al-HfO2, Gd-HfO2 and SBT), this work presents optimum guidelines to sustain internal amplification in planar and nanowire MFIS transistors. Graphic abstract: [Figure not available: see fulltext.]. © 2021, The Author(s), under exclusive licence to The Materials Research Society.