A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture

Abstract

Reconfigurability is an important capability that provides flexibility in computing architecture and low-power technique. It is challenging in digital-in-concept for designing smart analog circuits operated on low power. This work presents a low-power, low-noise, and high-speed multistage feed-forward reconfigurable comparator for medium-to-high-speed analog-to-digital converter. A power-efficient reconfigurable comparator design at 180 nm is presented with a new power reduction and offset compensation technique. The proposed dynamic latch-based 2-stage comparator gives an 83.2% power saving compared with a 3-stage comparator. The reduced number of active stages in comparator lowers the load capacitance to the post-amplifier and the power consumption. The 2-stage comparator gives a high slew rate, low power consumption, and better result at a Nyquist rate of 2.4 GS/s as compared with the previous state of the art. We have also proposed the reconfigurable multistage comparator, which gives the features of both 2-/3-stage comparators. We have performed the post-layout simulation to validate the design for process variation and mismatch with proposed circuit and compared with state of the art. Further, the voltage gain is 100 dB with power supply 1.8 V while consuming 523.4 μ W and 86.15 μ W for 3-stage and 2-stage comparator, respectively. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.