Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications

Abstract

Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the limited silicon area. In this work, a symmetric tri-state D flip-flop based lightweight PUF is proposed with increased uniqueness. The proposed architecture is implemented using a standard 40 nm CMOS technology. The post-layout simulation results show that it offers a uniqueness of 0.4994, which is the highest among all the considered architectures. Compared to the Arbiter PUF the proposed architecture has 0.267 × , 0.064 × , and 0.043 × less, power, silicon area, and energy per bit, respectively. Similarly, when compared with the Ring Oscillator PUF, the proposed architecture has 0.017 × , 0.031 × , and 0.0005 × less, power, silicon area, and energy per bit, respectively. Also, unlike other flip-flop based PUF, the proposed one does not require any post-processing block to remove the bias, thus contributes to saving the total implementation area and power of the system. An FPGA implementation is also presented as a proof-of-concept to verify functional correctness. For a better performance comparison among the considered architectures, a novel figure of merit (FOM) considering power, reliability, delay, silicon area, and uniqueness has been proposed, and it is observed that the proposed architecture offers the highest FOM among considered PUF architectures. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.