Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5733
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dc.contributor.authorBohara, Poojaen_US
dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:43:34Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:43:34Z-
dc.date.issued2019-
dc.identifier.citationBohara, P., & Vishvakarma, S. K. (2019). NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention. Journal of Computational Electronics, 18(2), 500-508. doi:10.1007/s10825-018-01298-9en_US
dc.identifier.issn1569-8025-
dc.identifier.otherEID(2-s2.0-85060095110)-
dc.identifier.urihttps://doi.org/10.1007/s10825-018-01298-9-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5733-
dc.description.abstractIn this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 10 3 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.en_US
dc.language.isoenen_US
dc.publisherSpringer New York LLCen_US
dc.sourceJournal of Computational Electronicsen_US
dc.subjectCellsen_US
dc.subjectCytologyen_US
dc.subjectFlash memoryen_US
dc.subjectNAND circuitsen_US
dc.subjectNitridesen_US
dc.subjectSemiconductor storageen_US
dc.subjectSilicon on insulator technologyen_US
dc.subjectSilicon oxidesen_US
dc.subjectThreshold voltageen_US
dc.subjectBuried oxidesen_US
dc.subjectDrain induced barrier lowering (DIBL)en_US
dc.subjectPhysical phenomenaen_US
dc.subjectShort-channel effecten_US
dc.subjectShort-channel performanceen_US
dc.subjectSilicon on insulator (SOI)en_US
dc.subjectSilicon oxide nitride oxide siliconsen_US
dc.subjectSubthreshold slopeen_US
dc.subjectMemory architectureen_US
dc.titleNAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retentionen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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