1T-DRAM with Shell-Doped Architecture

Abstract

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness ({T}-{\textsf {Shell}}) of 2 nm yields maximum retention. An SD ({N}-{\mathrm {d}}) of 10^{18} cm ^{-\textsf {3}} attains RT of 5.5 s and 630 ms at 27 °C and 85 °C, respectively, whereas higher {N}-{\textsf {d}} (10^{19} cm ^{-\textsf {3}} shows RT of 13ms at 85 °C for {L}-{\textsf {g}} = \textsf {200} nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of 11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. © 1963-2012 IEEE.