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DC Field | Value | Language |
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dc.contributor.author | Sharma, Vishal | en_US |
dc.contributor.author | Gopal, Maisagalla | en_US |
dc.contributor.author | Singh, Pooran | en_US |
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:44:22Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:44:22Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | Sharma, V., Gopal, M., Singh, P., & Vishvakarma, S. K. (2018). A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for internet of things (IoT) applications. AEU - International Journal of Electronics and Communications, 87, 144-157. doi:10.1016/j.aeue.2018.01.030 | en_US |
dc.identifier.issn | 1434-8411 | - |
dc.identifier.other | EID(2-s2.0-85043473663) | - |
dc.identifier.uri | https://doi.org/10.1016/j.aeue.2018.01.030 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5854 | - |
dc.description.abstract | In this work, a 9T subthreshold SRAM cell is proposed with the reduced leakage power and improved stability against the PVT variations. The proposed cell employs the read decoupling to improve the read stability, and the partial feedback cutting approach to control the leakage power with improved read/write ability. The incorporated stacking effect further improves the leakage power. The simulated leakage power for the proposed cell is 0.61×, 0.49×, 0.80× and 0.55×, while the read static noise margin (RSNM) is 2.5×, 1×, 1.05× and 0.96×, write static noise margin (WSNM) 0 is 1.5×, 1.8×, 1.68× and 1.9× and WSNM 1 is 0.95×, 1.2×, 1.05×, and 1.2× at 0.4 V when compared with the conventional 6T and state of arts (single ended 6T, PPN based 10T and data aware write assist (DAWA) 12T SRAM architectures) respectively. The minimum supply voltage at which this cell can successfully operate is 220 mV. A 4 Kb memory array has also been simulated using proposed cell and it consumes 0.63×, 0.67× and 0.63× less energy than 6T during read, write 1 and write 0 operations respectively for supply voltage of 0.3 V. © 2018 Elsevier GmbH | en_US |
dc.language.iso | en | en_US |
dc.publisher | Elsevier GmbH | en_US |
dc.source | AEU - International Journal of Electronics and Communications | en_US |
dc.subject | Cells | en_US |
dc.subject | Cytology | en_US |
dc.subject | Feedback | en_US |
dc.subject | Integrated circuits | en_US |
dc.subject | Internet of things | en_US |
dc.subject | Low power electronics | en_US |
dc.subject | Memory architecture | en_US |
dc.subject | Random access storage | en_US |
dc.subject | Internet of Things (IOT) | en_US |
dc.subject | Leakage power | en_US |
dc.subject | Partial feedback | en_US |
dc.subject | Read static noise margin (RSNM) | en_US |
dc.subject | Static noise margin | en_US |
dc.subject | Static random access memory | en_US |
dc.subject | Subthreshold sram cells | en_US |
dc.subject | Ultra low power | en_US |
dc.subject | Static random access storage | en_US |
dc.title | A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Electrical Engineering |
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