Hysteresis free negative total gate capacitance in junctionless transistors

Abstract

In this work, we report on the hysteresis free impact ionization induced off-to-on transition while preserving sub-60 mV/decade Subthreshold swing (S-swing) using asymmetric mode operation in double gate silicon (Si) and germanium (Ge) junctionless (JL) transistor. It is shown that sub-60 mV/decade steep switching due to impact ionization implies a negative value of the total gate capacitance. The performance of asymmetric gate JL transistor is compared with symmetric gate operation of JL device, and the condition for hysteresis free current transition with a sub-60 mV/decade switching is analyzed through the product of current density (J) and electric field (E). It is shown that asymmetric gate operation limits the degree of impact ionization inherent in the semiconductor film to levels sufficient for negative total gate capacitance but lower than that required for the occurrence of hysteresis. The work highlights new viewpoints related to the suppression of hysteresis associated with steep switching JL transistors while maintaining S-swing within the range 6-15 mV/decade leading to the negative value of total gate capacitance. © 2017 IOP Publishing Ltd.