Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5999
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dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:45:27Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:45:27Z-
dc.date.issued2017-
dc.identifier.citationGupta, D., & Vishvakarma, S. K. (2017). Improvement of short channel performance of junction-free charge trapping 3D NAND flash memory. Micro and Nano Letters, 12(1), 64-68. doi:10.1049/mnl.2016.0641en_US
dc.identifier.issn1750-0443-
dc.identifier.otherEID(2-s2.0-85007371672)-
dc.identifier.urihttps://doi.org/10.1049/mnl.2016.0641-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5999-
dc.description.abstractThis work investigates the effect of channel engineering on the short channel performance of considered sub-20-nm 3D NAND flash memory. Here, the threshold voltage roll-off (ΔVth), subthreshold swing and drain induced barrier lowering metrics is studied to evaluate the short channel effects (SCEs) for the examined device. The effect of variation in doping density on SCEs of proposed channel engineered NAND flash memory is also studied. Based on the observation, a thin layer of high doping concentration in the centre of the channel, covering 25% of channel area, has been found to improve the SCE of NAND flash memory compared with the device with uniform channel doping while maintaining sufficient drive current. © The Institution of Engineering and Technology 2016.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceMicro and Nano Lettersen_US
dc.subjectMemory architectureen_US
dc.subjectMOS devicesen_US
dc.subjectNAND circuitsen_US
dc.subjectThreshold voltageen_US
dc.subject3-d nand flash memoryen_US
dc.subjectChannel engineeringen_US
dc.subjectDoping concentrationen_US
dc.subjectDrain-induced barrier loweringen_US
dc.subjectShort-channel effecten_US
dc.subjectShort-channel performanceen_US
dc.subjectSubthreshold swingen_US
dc.subjectThreshold voltage roll-offen_US
dc.subjectFlash memoryen_US
dc.subjectArticleen_US
dc.subjectdepletionen_US
dc.subjectdiffusionen_US
dc.subjectdopingen_US
dc.subjectelectric potentialen_US
dc.subjectmemoryen_US
dc.subjectmemory cellen_US
dc.subjectphysical modelen_US
dc.subjectretention timeen_US
dc.subjectscale upen_US
dc.subjectsimulationen_US
dc.titleImprovement of short channel performance of junction-free charge trapping 3D NAND flash memoryen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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