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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:45:37Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:45:37Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | Gupta, D., & Vishvakarma, S. K. (2016). Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Transactions on Device and Materials Reliability, 16(3), 298-303. doi:10.1109/TDMR.2016.2578961 | en_US |
dc.identifier.issn | 1530-4388 | - |
dc.identifier.other | EID(2-s2.0-84986575911) | - |
dc.identifier.uri | https://doi.org/10.1109/TDMR.2016.2578961 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/6019 | - |
dc.description.abstract | In this paper, we investigate a new physical phenomenon for short-channel NAND Flash memory devices. Herein, we intend to examine the effect of lightly doped drain (LDD) depth variations on the 'ON ' current after the erase operation and the erase speed of the short-channel SONOS device. Additionally, we also investigate the electron trap density (residual charge) in charge trap (CT) layer after erase operation and its effect on the device erase characteristics. Furthermore, we carry out the simulation to find the effect of residual charge on the device endurance and the program performance of a SONOS device. Based on our results, the effect of residual charge on the 'ON' current after the erase operation that becomes smaller as the LDD depth increases. This phenomenon is contrary to the result of higher residual charge in the CT layer with a higher LDD depth and explained from device physics. Furthermore, program performance is found to be degraded with the presence of high residual charge. © 2016 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | IEEE Transactions on Device and Materials Reliability | en_US |
dc.subject | Drain current | en_US |
dc.subject | Memory architecture | en_US |
dc.subject | NAND circuits | en_US |
dc.subject | Electron trap density | en_US |
dc.subject | Lightly doped drains | en_US |
dc.subject | On currents | en_US |
dc.subject | Performance characteristics | en_US |
dc.subject | Physical phenomena | en_US |
dc.subject | Program performance | en_US |
dc.subject | Residual charge | en_US |
dc.subject | SONOS | en_US |
dc.subject | Flash memory | en_US |
dc.title | Impact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Device | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Electrical Engineering |
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