Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6019
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dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:45:37Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:45:37Z-
dc.date.issued2016-
dc.identifier.citationGupta, D., & Vishvakarma, S. K. (2016). Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Transactions on Device and Materials Reliability, 16(3), 298-303. doi:10.1109/TDMR.2016.2578961en_US
dc.identifier.issn1530-4388-
dc.identifier.otherEID(2-s2.0-84986575911)-
dc.identifier.urihttps://doi.org/10.1109/TDMR.2016.2578961-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6019-
dc.description.abstractIn this paper, we investigate a new physical phenomenon for short-channel NAND Flash memory devices. Herein, we intend to examine the effect of lightly doped drain (LDD) depth variations on the 'ON ' current after the erase operation and the erase speed of the short-channel SONOS device. Additionally, we also investigate the electron trap density (residual charge) in charge trap (CT) layer after erase operation and its effect on the device erase characteristics. Furthermore, we carry out the simulation to find the effect of residual charge on the device endurance and the program performance of a SONOS device. Based on our results, the effect of residual charge on the 'ON' current after the erase operation that becomes smaller as the LDD depth increases. This phenomenon is contrary to the result of higher residual charge in the CT layer with a higher LDD depth and explained from device physics. Furthermore, program performance is found to be degraded with the presence of high residual charge. © 2016 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Transactions on Device and Materials Reliabilityen_US
dc.subjectDrain currenten_US
dc.subjectMemory architectureen_US
dc.subjectNAND circuitsen_US
dc.subjectElectron trap densityen_US
dc.subjectLightly doped drainsen_US
dc.subjectOn currentsen_US
dc.subjectPerformance characteristicsen_US
dc.subjectPhysical phenomenaen_US
dc.subjectProgram performanceen_US
dc.subjectResidual chargeen_US
dc.subjectSONOSen_US
dc.subjectFlash memoryen_US
dc.titleImpact of LDD Depth Variations on the Performance Characteristics of SONOS NAND Flash Deviceen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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