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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6023
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dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:45:39Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:45:39Z-
dc.date.issued2016-
dc.identifier.citationBeohar, A., & Vishvakarma, S. K. (2016). Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width. Micro and Nano Letters, 11(8), 443-445. doi:10.1049/mnl.2016.0202en_US
dc.identifier.issn1750-0443-
dc.identifier.otherEID(2-s2.0-84982938756)-
dc.identifier.urihttps://doi.org/10.1049/mnl.2016.0202-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6023-
dc.description.abstractA comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high ION (6.9 × 10-4 A/μm), low IOFF (2.5 × 10-17 A/μm), and an enhanced ION/IOFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET. © 2016 The Institution of Engineering and Technology.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceMicro and Nano Lettersen_US
dc.subjectElectric resistanceen_US
dc.subjectGallium alloysen_US
dc.subjectChannel junctionsen_US
dc.subjectComparative studiesen_US
dc.subjectFringing fieldsen_US
dc.subjectGate-all-arounden_US
dc.subjectHigh series resistancesen_US
dc.subjectPerformance enhancementsen_US
dc.subjectSubthreshold swingen_US
dc.subjectTunnel field effect transistoren_US
dc.subjectField effect transistorsen_US
dc.subjectArticleen_US
dc.subjectcontrolled studyen_US
dc.subjectcurrent densityen_US
dc.subjectelectric potentialen_US
dc.subjectelectronen_US
dc.subjectenergyen_US
dc.subjectfield effect transistoren_US
dc.subjectphononen_US
dc.subjectsimulationen_US
dc.titlePerformance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer widthen_US
dc.typeJournal Articleen_US
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