Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6044
Full metadata record
DC FieldValueLanguage
dc.contributor.authorSingh, Pooranen_US
dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:45:49Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:45:49Z-
dc.date.issued2016-
dc.identifier.citationVijayvargiya, V., Reniwal, B. S., Singh, P., & Vishvakarma, S. K. (2016). Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications. Electronics Letters, 52(7), 559-560. doi:10.1049/el.2015.3797en_US
dc.identifier.issn0013-5194-
dc.identifier.otherEID(2-s2.0-84962382632)-
dc.identifier.urihttps://doi.org/10.1049/el.2015.3797-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6044-
dc.description.abstractTunnel field effect transistor (TFET) is being considered as an alternative to the conventional MOSFETs for low power system on chip applications. In this Letter, gate-drain underlap (UL) feature of double gate TFET for analogue/RF characteristic is discussed. Here, it is found that parasitic resistance induced by gate drain UL is not significant as compared with DG tunnel field effect transistor (DG-FET). Thus, the behaviour of RF figure of merit is different from DG-FET. © 2016 The Institution of Engineering and Technology.en_US
dc.language.isoenen_US
dc.publisherInstitution of Engineering and Technologyen_US
dc.sourceElectronics Lettersen_US
dc.subjectApplication specific integrated circuitsen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectSystem-on-chipen_US
dc.subjectConventional MOSFETsen_US
dc.subjectDouble gateen_US
dc.subjectFigure of meritsen_US
dc.subjectGate drainen_US
dc.subjectLow power applicationen_US
dc.subjectLow-power systemsen_US
dc.subjectParasitic resistancesen_US
dc.subjectTunnel field effect transistoren_US
dc.subjectField effect transistorsen_US
dc.titleAnalogue/RF performance attributes of underlap tunnel field effect transistor for low power applicationsen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetric Badge: