Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/6062
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kushwaha, C. B. | en_US |
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:45:58Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:45:58Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | Kushwah, C. B., & Vishvakarma, S. K. (2016). A single-ended with dynamic feedback control 8T subthreshold SRAM cell. IEEE Transactions on very Large Scale Integration (VLSI) Systems, 24(1), 373-377. doi:10.1109/TVLSI.2015.2389891 | en_US |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.other | EID(2-s2.0-84921988310) | - |
dc.identifier.uri | https://doi.org/10.1109/TVLSI.2015.2389891 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/6062 | - |
dc.description.abstract | A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of isoarea 6T and read-decoupled 8T (RD-8T), respectively, at 300 mV. The standard deviation of write SNM for 8T cell is reduced to 0.4×and 0.56×as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM ∼ 2.33×, 1.23×, and 0.89×as that of 5T, 6T, and RD-8T, respectively. The cell has hold SNM of 1.43×, 1.23×, and 1.05×as that of 5T, 6T, and RD-8T, respectively. The write time is 71% lesser than that of single-ended asymmetrical 8T cell. The proposed 8T consumes less write power 0.72×, 0.6×, and 0.85× as that of 5T, 6T, and isoarea RD-8T, respectively. The read power is 0.49× of 5T, 0.48× of 6T, and 0.64×of RD-8T. The power/energy consumption of 1-kb 8T SRAM array during read and write operations is 0.43× and 0.34×, respectively, of 1-kb 6T array. These features enable ultralow power applications of 8T. © 2015 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | en_US |
dc.subject | Cells | en_US |
dc.subject | Cytology | en_US |
dc.subject | Energy gap | en_US |
dc.subject | Feedback control | en_US |
dc.subject | Random access storage | en_US |
dc.subject | T-cells | en_US |
dc.subject | Data stabilities | en_US |
dc.subject | Standard deviation | en_US |
dc.subject | Static noise margin | en_US |
dc.subject | Static random access memory | en_US |
dc.subject | Subthreshold operation | en_US |
dc.subject | Subthreshold sram cells | en_US |
dc.subject | Ultralow power application | en_US |
dc.subject | Write operations | en_US |
dc.subject | Static random access storage | en_US |
dc.title | A Single-Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Electrical Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: