Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6112
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dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:46:23Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:46:23Z-
dc.date.issued2014-
dc.identifier.citationVijayvargiya, V., & Vishvakarma, S. K. (2014). Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Transactions on Nanotechnology, 13(5), 974-981. doi:10.1109/TNANO.2014.2336812en_US
dc.identifier.issn1536-125X-
dc.identifier.otherEID(2-s2.0-84958111725)-
dc.identifier.urihttps://doi.org/10.1109/TNANO.2014.2336812-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6112-
dc.description.abstractIn this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (I rm ON), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (g m), unit-gain cutoff frequency (f-T), maximum frequency of oscillation $(f-), and gain bandwidth product. For this, the RF figures of merit have been extracted from the Y-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA. © 2002-2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Transactions on Nanotechnologyen_US
dc.subjectCapacitanceen_US
dc.subjectComputer aided designen_US
dc.subjectCutoff frequencyen_US
dc.subjectDrain currenten_US
dc.subjectElectron tunnelingen_US
dc.subjectGates (transistor)en_US
dc.subjectLogic gatesen_US
dc.subjectMOS devicesen_US
dc.subjectRadio wavesen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectSilicon on insulator technologyen_US
dc.subjectDoping profilesen_US
dc.subjectGain-bandwidth productsen_US
dc.subjectGate-drain capacitanceen_US
dc.subjectMaximum frequency of oscillationsen_US
dc.subjectPerformance evaluationen_US
dc.subjectRadio frequenciesen_US
dc.subjectTechnology computer aided designen_US
dc.subjectTunnel field effect transistoren_US
dc.subjectField effect transistorsen_US
dc.titleEffect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performanceen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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