Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6145
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:46:41Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:46:41Z-
dc.date.issued2012-
dc.identifier.citationSingh Parihar, M., Ghosh, D., Alastair Armstrong, G., & Kranti, A. (2012). Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory. Applied Physics Letters, 101(26) doi:10.1063/1.4773055en_US
dc.identifier.issn0003-6951-
dc.identifier.otherEID(2-s2.0-84871730949)-
dc.identifier.urihttps://doi.org/10.1063/1.4773055-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6145-
dc.description.abstractIn this work, we analyze the snapback effect and extract the effective bipolar current gain in junctionless nanotransistors. The optimal electron and hole concentrations required to trigger and sustain bipolar snapback in junctionless transistors have been evaluated. The occurrence of snapback at lower drain bias (≅ 2 V) in junctionless devices in comparison to conventional inversion mode transistors demonstrates the enormous potential for static power reduction in capacitorless dynamic random access memories. High values (40-70) of effective bipolar current gain achieved in optimally designed junctionless transistors can be utilized to improve the sensing margin for dynamic memories. © 2012 American Institute of Physics.en_US
dc.language.isoenen_US
dc.sourceApplied Physics Lettersen_US
dc.subjectBipolar currentsen_US
dc.subjectBipolar snapbacken_US
dc.subjectCapacitorless dynamic random access memoriesen_US
dc.subjectDrain biasen_US
dc.subjectDynamic memoryen_US
dc.subjectInversion modesen_US
dc.subjectJunctionlessen_US
dc.subjectNano transistorsen_US
dc.subjectSensing marginen_US
dc.subjectStatic power reductionen_US
dc.subjectCapacitorsen_US
dc.subjectStrontium compoundsen_US
dc.subjectTransistorsen_US
dc.titleBipolar snapback in junctionless transistors for capacitorless dynamic random access memoryen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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