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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/9774
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dc.contributor.authorGupta, Anupreeten_US
dc.contributor.authorAnwer, Hajraen_US
dc.contributor.authorReniwal, Bhupendra Singhen_US
dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-05-05T15:43:20Z-
dc.date.available2022-05-05T15:43:20Z-
dc.date.issued2014-
dc.identifier.citationGupta, A., Anwer, H., Reniwal, B. S., & Vishvakarma, S. K. (2014). Analysis of stability issues and power efficiency of symmetric and asymmetric low power nanoscaled SRAM cells. Paper presented at the Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS, doi:10.1109/ICDCSyst.2014.6926149 Retrieved from www.scopus.comen_US
dc.identifier.isbn978-1479913565-
dc.identifier.issn1541-6275-
dc.identifier.otherEID(2-s2.0-84908305778)-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/9774-
dc.identifier.urihttps://doi.org/10.1109/ICDCSyst.2014.6926149-
dc.description.abstractOver the period of advancements in technology, stability and power-efficiency of the memory cells have proven to be the dire urges. And this has led to the development of various static memory cell topologies. In this paper, analysis of very important factors of merits of Static Random Access Memory (SRAM) i.e. Static Noise Margin (SNM) and total power consumption in 6T, 8T and 5T SRAM cells designed at 65nm UMC CMOS technology is done. The work includes a vivid description of the factors like applied voltage (Vdd) and different process corners affecting the SNMs and power consumption variations along with the simulations. The simulations are well in agreement with the expectations based on the different cell structures and their functionalities. © 2014 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceProceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCSen_US
dc.subjectCells|Cytology|Efficiency|Electric power utilization|Semiconductor storage|Analysis of stability|Dynamic Power|Power consumption variations|Static memory cells|Static noise margin|Static power|Static random access memory|Total power consumption|Static random access storageen_US
dc.titleAnalysis of stability issues and power efficiency of symmetric and asymmetric low power nanoscaled SRAM cellsen_US
dc.typeConference Paperen_US
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