Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/1002
| Title: | Reducing the error in patterns fabricated on the silicon wafers |
| Authors: | Reddy, Amarnath Dey, Somnath [Guide] |
| Keywords: | Computer Science |
| Issue Date: | 10-Dec-2017 |
| Publisher: | Discipline of Computer Science and Engineering, IIT Indore |
| Series/Report no.: | BTP292;CSE 2017 RED |
| URI: | https://dspace.iiti.ac.in/handle/123456789/1002 |
| Type of Material: | B.Tech Project |
| Appears in Collections: | Department of Computer Science and Engineering_BTP |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| BTP_292_Amarnath_Reddy_140001019.pdf | 876.13 kB | Adobe PDF |  View/Open |
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