Sensitivity implications for programmable transistor based 1T-DRAM

Abstract

In this letter, we report an insightful evaluation of the base performance and sensitivity of 1T-DRAM implemented through a programmable or reconfigurable transistor (RFET). Although RFET based 1T-DRAM exhibits enhanced retention time (>64 ms at 85 °C and 125 °C) with an appreciable sense margin (∼16 µA/µm) and total length scalability down to 50 nm, metrics are sensitive to biases, parameter variations and traps. RFET exhibiting highest retention is expected to offer a relatively narrow operating window (~75 mV) for read bias. This stringent criterion can be relaxed with a wider read bias window (~150 mV) in RFET architectures exhibiting retention lower than maximum but still higher than >64 ms. © 2022 Elsevier Ltd