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https://dspace.iiti.ac.in/handle/123456789/10131
| Title: | Sensitivity implications for programmable transistor based 1T-DRAM |
| Authors: | Nirala, Rohit Kumar Semwal, Sandeep Bhuvaneshwari, Y. V. Rai, Nivedita Kranti, Abhinav |
| Keywords: | C (programming language);1t drams;Generation;Performance;Programmable (reconfigurable) transistor;Recombination;Reconfigurable transistors;Retention time;Schottky barriers;Sense margin;Sensitivity;Schottky barrier diodes |
| Issue Date: | 2022 |
| Publisher: | Elsevier Ltd |
| Citation: | Nirala, R. K., Semwal, S., Bhuvaneshwari, Y. V., Rai, N., & Kranti, A. (2022). Sensitivity implications for programmable transistor based 1T-DRAM. Solid-State Electronics, 194, 108353. https://doi.org/10.1016/j.sse.2022.108353 |
| Abstract: | In this letter, we report an insightful evaluation of the base performance and sensitivity of 1T-DRAM implemented through a programmable or reconfigurable transistor (RFET). Although RFET based 1T-DRAM exhibits enhanced retention time (>64 ms at 85 °C and 125 °C) with an appreciable sense margin (∼16 µA/µm) and total length scalability down to 50 nm, metrics are sensitive to biases, parameter variations and traps. RFET exhibiting highest retention is expected to offer a relatively narrow operating window (~75 mV) for read bias. This stringent criterion can be relaxed with a wider read bias window (~150 mV) in RFET architectures exhibiting retention lower than maximum but still higher than >64 ms. © 2022 Elsevier Ltd |
| URI: | https://doi.org/10.1016/j.sse.2022.108353 https://dspace.iiti.ac.in/handle/123456789/10131 |
| ISSN: | 0038-1101 |
| Type of Material: | Journal Article |
| Appears in Collections: | Department of Electrical Engineering |
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