Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/10325
Title: Enabling sub-Boltzmann on-to-off switching through metal-ferroelectric-metal-insulator-semiconductor architecture
Authors: Gaitonde, Digamber Anil
Supervisors: Kranti, Abhinav
Keywords: Electrical Engineering
Issue Date: 6-Jun-2022
Publisher: Department of Electrical Engineering, IIT Indore
Series/Report no.: MT181
Abstract: In order to meet the computational demands, high-density chips are required. A larger number of transistors on a single integrated chip allows greater functionality to be packed in a given module and also lowers the cost for the chip manufacturers. The way to achieve such high-density chips is by downscaling or reducing the dimensions of the transistors. However, reducing the dimension affects the transistor performance i.e, formation of an ultra-sharp p-n junction, Short channel effects (SCEs), static power dissipation, and poor on to off current ratio,. In order to meet the high on to off current ratio requirement at lower supply voltages, several transistor architectures such as Impact ionization MOS (IMOS), Tunnel FET (TFET), Feedback FET, and Negative capacitance FET have been proposed in the literature. These structures have different conduction mechanisms and involve p-n junction formation which makes the fabrication process very complex and costly as lower technology nodes. The formation of p-n junction can be avoided using the junctionless (JL) topology, which consists of the entire film doped with the same type of dopants. Although it provides better subthreshold characteristics and scalability. However, it has some limitations such as the requirement for high work function to deplete the heavily doped film in the off state. These limitations can be overcome by stacking the ferroelectric (FE) layer over the gate terminal of the JLFET. the with the negative capacitance (NC) phenomenon of FE materials. A FE layer with negative capacitance results in a negative internal gate voltage at zero control gate bias, which results in depletion of heavily doped film at a midgap work function. Also, utilizing the negative capacitance phenomena of the FE layer, a sub-60 mV/dec subthreshold swing can be attained with the suppressed short channel, which makes an NC JLFET a potential candidate for ultralow-power and high-density applications.
URI: https://dspace.iiti.ac.in/handle/123456789/10325
Type of Material: Thesis_M.Tech
Appears in Collections:Department of Electrical Engineering_ETD

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