Logic-in-memory computing using RRAM based NV-SRAM

Abstract

Semiconductor Industries are dealing with the continual influx of accessible data and the never-ending requirements for better and quicker performance to maintain a competitive advantage and fulfil today’s needs for an ideal user experience. In-Memory Computing(IMC) is gaining traction as a result of this. Because IMC is more about how much data can be absorbed and evaluated in a short amount of time. Incorporating alternate memory technologies, such as nonvolatile memory, is an important trend for IMC since it allows for multilayer storage, higher density, and low-power duty-cycle operation. Static Random Access Memory (SRAM), Re sistive RAM (RRAM), and phase-change memory(PCM) are examples of trending memory technologies. RRAM-based architectures are proving themselves as a well established storage method.Because of its simple structure, compatibility with ex isting CMOS technology, high switching speed, and ability to scale to the tiniest dimensions, RRAM is one of the most intriguing memory technologies. In this thesis Logic-In-Memory designs have been proposed using IHP 130nm RRAM technology. Combinational circuits like NOR, NAND, XOR have been suc cessfully simulated and optimized in terms of operating power and speed of oper ation. These designs are hybrid as it is incorporated with 130nm CMOS transis tor technology to achieve better functionality. Further, Non-Volatile SRAM(NV SRAM) cell is proposed which is a combination of 6T-SRAM and RRAM to incor porate non-volatility feature. Using this 8T1R NV-SRAM, a 4-cell array has been designed with all the peripherals such as Sense Amplifier, Decoder, Bitline Driver and others. Lastly, A PMOS-based voltage reference generator is proposed which makes the reference generation stage less susceptible towards small variations in incoming voltage (in the order of uV ) as the Loading Effect (LE) grows at the input of the comparator stage in ADC in any memory(RRAM) array. The circuit stability is evaluated for process variation and device mismatch. Further, sleep mode is applied using the power-gating (PG) technique to minimize power dissipation.