Lagrangian Heuristics based parallel FPGA router

Abstract

Field-Programmable Gate Arrays (FPGA) are re-programmable chips used extensively in many areas. As per Moore’s Law, the number of transistors in an integrated circuit are dou bling approximately every two years. Due to this exponential increase, there is an increasing delay in the FPGA CAD (Computer-Aided Design) Flow Process. Also, there is an increase in the run-time of FPGA, as interconnection delays are much more than logic delays of a circuit implemented in an FPGA. So, we need to develop better and efficient routing algorithms. The most commonly used routing algorithm is VPR (Vertical Place and Route). It routes effectively, but is slow in execution. One way to speed up the routing process is to use paral lelization. Since VPR is intrinsically sequential, it cannot be parallelized. Lately, a set of parallel algorithms (ParaLaR and ParaLarPD) were proposed. These algorithms formulated the FPGA Routing problem as a Linear Programming (LP) minimization problem. The dependencies that hinder the nets from routing in parallel are investigated and relaxed using Lagrange Relaxation in this LP. The sub-gradient approach and the Steiner tree algorithm are used to solve the re laxed LP in parallel. The drawback of these algorithms is that they were implemented using VPR7.0 Framework (recently VPR8.0 framework was released), the minimum channel width metric further needs to be improved (which indirectly reduces constraints violations) and they were evaluated on smaller and older benchmarks. The goal of this thesis is to overcome these drawbacks. That is, the objectives are to migrate to the latest version of VPR8.0, to develop a heuristics to reduce the channel width requirements thereby indirectly reducing the constraints violations, and to evaluate our proposed approach on larger benchmarks.