Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/10481
Title: Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression
Authors: Sengupta, Anirban
Chaurasia, Rahul
Keywords: Biometrics;Chromosomes;Cryptography;Digital signal processing;DNA;Internet protocols;Iterative methods;Biological cells;Biometric (access control);Cipher;DNA impression;Hardware;Intellectual property network;Obfuscation;Property networks;Security;Access control
Issue Date: 2022
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., & Chaurasia, R. (2022). Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression. IEEE Access, 10, 50903–50913. https://doi.org/10.1109/ACCESS.2022.3174349
Abstract: This paper presents a novel hybrid methodology with structural obfuscation and encrypted chromosomal DNA impression to secure intellectual property (IP) cores of digital signal processing (DSP) applications. The proposed work offers security against altering register transfer level (RTL) description using multilevel structural obfuscation as well as security against IP piracy using secret chromosomal DNA impression. In this approach, an invisible DNA impression is covertly implanted into the structurally obfuscated DSP design using robust encoding and encryption using multi-iteration Feistel cipher. Our work is more robust than recent facial biometric and steganography-based hardware IP security techniques, in terms of stronger proof of digital evidence as well as tamper tolerance ability. The results report following qualitative and quantitative analysis of the proposed structural obfuscation with encrypted chromosomal DNA impression based framework: (a) very low probability of coincidence (Pc) (indicating strength of digital evidence) for different DSP IP cores in the range of 7.59E-5 to 1.2E-1; (b) stronger tamper tolerance for different DSP IP cores in the range of 5.62E +14 to 3.40E +38; (c) negligible design cost overhead of 0.00% for different DSP IP cores; (d) strength of obfuscation in terms of number of gates obfuscated. © 2013 IEEE.
URI: https://doi.org/10.1109/ACCESS.2022.3174349
https://dspace.iiti.ac.in/handle/123456789/10481
ISSN: 2169-3536
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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