Ultra - low power high-stability robust sram design for FPGA, IoT and image processing applications

Abstract

The scaling of transistors helps to reduce the voltage and power required for reliable operation with improved functionality and performance of embedded memories. Moreover, in embedded memories, static random access memory (SRAM) is considered as a critical technology enabler for a wide range of applications. However, with the scaling of complementary metal oxide semiconductor (CMOS) technology, the conventional SRAMs have failed to achieve the trade-off between system power and performance for the applications in electronic devices such as portable smartphones, laptops, field programmable gate arrays (FPGAs), IoT edged devices and image processing systems. Therefore, the development of application-oriented SRAM architectures at ultra-low voltage (ULV) has emerged significantly. In addition, the key constraint in high-performance SRAM is the power consumption. The SRAM contributes to the largest share of power consumption in a digital system. However, in SRAM, power reduction can be achieved by scaling the supply voltage to the subthreshold region. Though, operations at subthreshold voltages degrade the robustness of system due to depleted noise margins and higher susceptibility to process variations. Another challenge in ULV SRAM is the statistical process variations in transistor parameters such as threshold voltage (Vth), channel length (L), and mobility. Therefore, the statistical device variability in modern SRAM design has become a major concern, as it degrades the performance, reliability, and yield of the system. Moreover, the noise generated from threshold variation, process variation, half-select issue and multiple bit errors reduces the stability of SRAM cell. Therefore, the SRAM instability at various process-voltagetemperature (PVT) values has also become a challenging issue. To overcome the aforementioned limitations, differential/single ended ultra-low power process tolerant SRAM architectures are presented in this thesis. The presented SRAMs provide a colossal amount of reduction in standby power, improvement in readwrite static noise margin, reduction in the read-write access time, reduction in the power delay product (PDP) or energy of SRAM and improvement in overall performance at different process-voltage-temperature (PVT) conditions. Moreover, in this thesis, applications of ultra-low power SRAMs in field programmable gate array (FPGA), internet of thing (IoT) edge devices and image processing are discussed. These applications have different requirements and hence, separate SRAM architectures are designed for each application. The FPGA block requires high-performance, low-leakage SRAM, therefore, a feedback controlled 10T SRAM is presented. The low-end IoT edge devices require high-stability energy-efficient SRAM, hence a process tolerant 10T SRAM is presented. For high-end IoT edge devices, a high-performance, high-stability and ultra-low power SRAM is needed, hence a write assist 10T SRAM is presented. However, for image processing systems, a smaller size, low power and high stability 8T SRAM is presented in the thesis. This, in turn, makes the proposed SRAM architectures robust and suitable for the application in FPGAs, IoT devices and image processing.