Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/10997
Title: A Novel Gain Enhanced Folded Cascode OPAMP in 28nm CMOS Technology
Authors: Hemantha Kumar, Ravi;Vishvakarma, Santosh Kumar;
Keywords: Analog circuits; Cascode amplifiers; CMOS integrated circuits; Signal processing; 28nm CMOS; CMOS technology; Folded cascade; Folded-cascode; Foldings; Gain; Mismatch; Noise; Output swing; Phase margins; Operational amplifiers
Issue Date: 2022
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Kumar, R., Nagulapalli, R., & Vishvakarma, S. K. (2022). A novel gain enhanced folded cascode OPAMP in 28nm CMOS technology. Paper presented at the International Conference on Electrical, Computer, and Energy Technologies, ICECET 2022, doi:10.1109/ICECET55527.2022.9872766 Retrieved from www.scopus.com
Abstract: Folded cascade Opamp is the preferred first stage choice in a typical two-stage opamp due to relaxed headroom and better output swing. Traditional Folded cascade opamp gain and noise are compromised due to the folding transistors. In this work, FVF assisted differential pair has been proposed which extracts the signal and injects it onto the gate of the folding devices, hence they will contribute gain and noise will be reduced. A prototype was developed in 2Snm TSMC CMOS technology and post-layout simulation results were performed. The proposed opamp achieves 68dB DC gain, which is 18dB higher than the conventional one. Also, the proposal exhibits 20% improvement in the input-referred noise for the same power consumption. Further, the circuit consumes 33W of power from a 1V power supply and occupies a 78∗46m2 silicon area. © 2022 IEEE.
URI: https://doi.org/10.1109/ICECET55527.2022.9872766
https://dspace.iiti.ac.in/handle/123456789/10997
ISBN: 978-1665470872
Type of Material: Conference Paper
Appears in Collections:Department of Electrical Engineering

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