Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

Abstract

High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1 T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (∼1 ns) and read (∼1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be a challenge for energy efficient system-on-chip applications. © 2023 The Japan Society of Applied Physics.