Performance assessment of tunneling based transisstors for capacitorless dynamic memory applications

Abstract

With the advent of Moore’s law and Dennard’s scaling theory, the performance of processor units in computers improved. However, the overall system performance which was based on the interaction between the processor and memory units, didn’t improve with the same pace due to the lack of focus on memory. Thus, in the last decade, the emphasis has been directed to enhance the speed and density of memory with operation at low power. This necessitated reduction in the size of the capacitor in the conventional Dynamic Random Access Memory (DRAM) based on one transistor and capacitor (1T-1C). However, capacitor scaling adversely affects the charge retention, requires more refresh cycles, and consequently, dissipates more power. The problem was circumvented with the introduction of the single transistor (1T) as DRAM cell. While conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) based 1T-DRAMs have shown promising results, the focus has shifted towards use of devices with potential to operate at low power. Thus, the thesis work focuses on an energy efficient device, Tunnel FET (TFET) as DRAM, improving its Retention Time (RT), Sense Margin (SM), speed, and scalability at low power.Through the TFET design presented in previous works, the RT achieved was lower than the target of 64 ms, specified by International Technology Roadmap for Semiconductors (ITRS). Therefore, a careful reinvestigation is required to enhance the RT of TFET based DRAM. The work in the thesis provides insights into the understanding of the performance and behaviour of TFET devices for memory applications by means of comprehensive physical device simulations. The key contribution of this research is to provide insights into the physical phenomenon occurring in the device, which influences the operation of TFET as dynamic memory. The thesis work demonstrates device perspective, where various metrics of DRAM are regulated by device architecture (misaligned, twin, and planar tri-gate TFET), geometry (gate lengths, film thickness), parameters (oxide thickness, gate workfunctions), biases and temperature. These govern hole generation and recombination in the storage region that defines distinct operations (write, read and hold) of DRAM.The functionality of TFET based dynamic memory is based on the distinct roles of the gates, where the first gate (G1), aligned to source at top surface, is utilized for read mechanism based on band-to-band tunneling, while the second gate (G2) is responsible for creation of a dedicated volume for charge storage. G2 is aligned to drain, positioned at the bottom, at the front un-gated region in misaligned DG, and at the front adjacent to the first gate in twin gate and planar tri-gate topologies. The non-overlapping of G1 and G2 result into a profound well formation that enhances the charge retention. The p+ poly G2 creates a deep potential well that sustains charges for longer duration. Results demonstrate RT in few seconds for all proposed architectures with length of G1 (Lg1) as 400 nm and length of G2 (Lg2) as 200 nm at 85 C, which shows a remarkable improvement over previously proposed structures.The drawback of low SM has been overcome through incorporation of a symmetric G1 as in planar tri-gate TFET. The improved electrostatic control of G1 over channel, improves the SM, and also, scalability of G1 (down to 25 nm) and drain voltage (0.8 V) with acceptable SM and RT in planar tri-gate topology. Exploring TFET for functionality at shorter gate lengths, the design optimization through incorporation of a lateral spacing between the gates (Lgap) and an underlap (Lun) between the drain and G2, can further enhance retention and scalability. While scaling G2 reduces RT, scaling G1 degrades SM. Therefore, an analysis of each individual length (Lg1, Lg2, Lgap, Lun) estimates the minimum length required to attain RT > 64 ms. While the total length (Ltotal = Lg1+ Lg2+ Lgap+ Lun) for misaligned DG and twin gate TFET can be scaled down to ~160 nm, planar tri-gate show an improved scalability down to ~115 nm. Other than improved SM and RT at reduced size and high temperature, functionality at lower drain voltage with low write time, nominates TFET for embedded applications.The work presented in the thesis showcases new viewpoints for TFET to function efficiently as dynamic memory. The physical insights and analysis of different attributes with optimal utilization of each lead to improved metrics as well as suppressed trade-offs. The systematic analysis through innovative approaches leads to capacity, retention, at low energy with operation at reduced size. The use of an energy optimized DRAM memory with RT > 64 ms is well-suited for standalone applications, and as well as, for integrated circuits embedded with logic devices.