Subthreshold CMOS circuit design with emerging transistor architectures

Abstract

Ultra low power (ULP) CMOS circuits are gaining wide attention in recent times due to the growing demand for battery-operated and energy- harvesting devices used in wearable electronics, IoT sensors, and implantable medical applications. ULP circuits help to maximize the battery life and reduce the frequency of battery replacement or recharging. An ULP Schmitt trigger (ST) circuit is a basic and important logic circuit block based on the positive feedback mechanism that is designed to operate with extremely low power consumption while providing hysteresis, which can be used in various applications such as i) signal conditioning and noise rejection purposes, ii) threshold detection, and waveform shaping, iii) timing circuits, clock generators, and waveform generation, iv) edge detection in digital systems, v) static random access memory (SRAM) circuit, vi) buffer circuit, and vii) sensors, etc. However, the implementation of high-density nanoscale ULP ST has several challenges such i) reduced on-to-off current ratio (Ion/Ioff) at low supply voltages which degrades the hysteresis width, ii) at lower gate lengths, leakage increases due to short channel effects, which limits the hysteresis width, and iii) a requirement of the larger number of transistors to implement ST circuit (6 transistors for conventional circuit).