Current and capacitance model of underlap double gate mosfet for ultra low power applications

Abstract

Ultra low power (ULP) CMOS circuits are gaining wide attention in recent times due to the growing demand for energy-harvesting devices. In ULP applications, supply voltage is limited to the threshold voltage of the transistor i.e. the transistor essentially operates in the subthreshold region. Thus, in ULP applications, the performance and speed of the circuit strongly depend on the subthreshold characteristics, extent of short channel effects (SCEs) and parasitic capacitance of the device. To overcome the SCEs, multi-gate transistors like double gate (DG) can be used, which can effectively suppress SCEs. However, a larger number of gates in DG MOSFET leads to a higher contribution of parasitic capacitance in the overall gate capacitance. This affects the circuit delay and operating speed of the ULP circuit. To overcome these challenges, DG MOSFET with underlap regions can be used. A larger separation between the heavily doped source/drain and the gate edge due to the underlap region significantly reduces parasitic capacitance. In addition, incorporating underlap in DG MOSFETs enhances short channel immunity by increasing the effective gate length.