Encoded encryption and biometrics for high-level synthesis based hardware security against IP piracy and fraud IP ownership

Abstract

This thesis presents two novel methodologies for securing intellectual property (IP) core designs against hardware security threats. The first methodology is a quadruple-phase watermarking technique for securing hardware IP cores during high-level synthesis (HLS). In contrast, the second methodology explores unified biometrics with an encoded dictionary for the hardware security of fault-secured digital signal processing (DSP) intellectual property (IP) core designs. The first methodology addresses the issue of IP piracy and ownership infringement that poses a significant threat to the security of authentic IP vendors. The proposed quadruple-phase watermarking technique employs graph portioning, encoding tree, and eightfold mapping to generate a robust watermarking signature. The signature is embedded at four stages of HLS, including scheduling, register binding, resource binding, and interconnect binding, to ensure high-quality hardware security constraints. The results demonstrate a considerable decrease in the probability of coincidence and a higher level of tamper tolerance compared to the state-of-the-art techniques without incurring a significant design cost overhead.