Insightful evaluation of advantages and challenges of reconfigurable transistor for analog/RF applications

Abstract

Over the last few years, the practice of reducing the size of transistors has reached a saturation point. This is primarily due to the severe influence of short channel effects (SCEs) such as drain induced barrier lowering (DIBL), threshold voltage (Vth) roll-off, etc., which significantly degrade the device performance when scaling down in the sub-100 nm regime. An alternative method for increasing the number of functions on a chip per unit area is to incorporate additional functionality within the same device, instead of reducing the device size. This is where Reconfigurable Field Effect Transistor (RFET) comes into play. The emergence of RFET, which can demonstrate both unipolar n-type and p-type functionality in a single device, has positioned itself as a robust rival to modern transistor architectures due to its exceptional performance at both device and circuit levels. RFET devices have shown promising results in a wide range of applications spanning from digital logic to trending topics like neuromorphic engineering. However, the effectiveness of RFET in analog/RF applications has not gained enough attention. To date, there exists a literature gap as only a limited number of studies have showcased the usefulness of RFET in the context of analog and RF applications. Research on analog/RF performance of RFET specifically at low current drives (ultra low power operation), has yet to be conducted. To become a prominent contender for modern mixed-signal applications (e.g. smartphones), RFET must not only enhance its digital characteristics, but also allocate comparable attention towards its analog functionality as well.