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https://dspace.iiti.ac.in/handle/123456789/12429
| Title: | Architecture Dependent Constraint-Aware RFET Based 1T-DRAM |
| Authors: | Semwal, Sandeep Nirala, Rohit Kumar Rai, Nivedita Kranti, Abhinav |
| Issue Date: | 2023 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Semwal, S., Nirala, R. K., Rai, N., & Kranti, A. (2023). Architecture Dependent Constraint-Aware RFET Based 1T-DRAM. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Scopus. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134488 |
| Abstract: | The constraints of retention time (TRet), speed, and power consumption at fixed total length (LSi =100 nm) and minimum bias levels (4) present bottlenecks in the operation of reconfigurable transistor (RFET) as capacitorless (1T) dynamic random access memory (DRAM). A constraint-aware assessment of 1T-DRAM showcases potential for high TRet=2.9 s with sense margin (SM) > 25 μ A μ m and current ratio (CR) > 102 at 85°C. Scaled down 1T-DRAM with LSi =50 nm exhibits a decent TRet(∼35 ms) at write (4 ns) and read (5 ns) time with SM= 40 μ A μ m and CR=103 which highlights prospects for embedded applications. Disturbance due to shared bit and word lines is also discussed. © 2023 IEEE. |
| URI: | https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134488 https://dspace.iiti.ac.in/handle/123456789/12429 |
| ISBN: | 979-8350334166 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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