Device design and analysis of 3D SCwRD cylindrical (Cyl) gate-all-around (GAA) tunnel FET using split-channel and spacer engineering

Abstract

The research under consideration explains a novel idea for a TFET that uses a gate-all-around (GAA) hetero-dielectric gate to minimize short channel effects (SCEs). To achieve high ION of 1.12 × 10−5 A/μm and robust IOFF of 4.12 × 10−18 A/μm at Vgs = 1.2 V, impacts of split channel with retrograde doping (SCwRD) gate-all-around (GAA)-TFET is proposed in this chapter. A technology computer-aided design (TCAD) 3D device computing program is used to model and calculate the analog/RF parameters of the proposed structure. A thorough analysis of AC, DC, and RF/analog parameters such as ON-current, OFF-current, energy band gap, Miller Capacitance (Gate-Drain Capacitance [Cgd]), Gate-Source Capacitance (Cgs), transconductance (gm), cutoff frequency (fT), maximum oscillation frequency (fmax), and gain bandwidth (fA) is presented. The suggested device threshold voltage is observed to be 0.35 V, and the subthreshold swing (SS) is 40.08 mV/decade. At drain source voltage (Vds) = 1 V, low values of the parameters, Cgd = 80 × 10−18 F Cgs = 0.25 fF, and gm = 58 μA/V, ft = 260 GHz, are achieved. © 2024 selection and editorial matter, Ankur Beohar, Ribu Mathew, Abhishek Kumar Upadhyay, and Santosh Kumar Vishvakarma -individual chapters, the contributors.