A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores [Feature]

Abstract

This paper presents a novel survey of high level synthesis (HLS) based hardware security approaches for reusable intellectual property (IP) cores used in consumer electronics and computing systems. A succinct review of all major HLS based hardware security approaches applied on reusable IP cores, along with their design flow and security analysis, is provided. The paper presents a detailed design flow of hardware integrated circuits (ICs) along with vulnerability points where potential attacks/threats are possible. Trustworthy and untrustworthy regimes in the design flow have also been highlighted in the discussion. Further, a discussion of detective and preventive control-based HLS hardware security approaches used for hardware IP cores has also been presented, including an analysis of prominent structural obfuscation, logic locking (logic encryption), and IP core protection (IPP) techniques. Each approach has been lucidly explained in terms of its threat model, algorithm, and security analysis. Finally, a security comparison of hardware IP obfuscation approaches in terms of strength of obfuscation security metric as well as a security comparison of IPP approaches in terms of probability of coincidence security metric, have also been introduced. © 2001-2012 IEEE.