Hardware-efficient and performace-enhanced MAC unit for DNN applications: a quantization approach

Abstract

Artificial Intelligence (AI) has witnessed remarkable growth, garnering significant attention from various industries and researchers due to its extensive applications. Researchers continuously explore different types of Deep Neural Networks (DNNs) and their efficient implementations using diverse techniques and datasets for various use cases, encompassing software-level applications to hardware-level systems. Edge- AI Systems-on-Chip (SoCs) is a focal point for industries, tailored to specific customer applications rather than generic CPU or GPU designs. As a result, these edge-AI devices are optimized to perform particular functions, allowing customization of hardware to focus on specific performance parameters. For instance, applications that require low power, small area, and high accuracy. The MAC unit plays a crucial role in the convolution operation, making its physical parameters vital for efficient overall design implementation. Typically, the MAC unit consists of a multiplier followed by an accumulator. The multiplier’s bit-width is twice that of its input, and the accumulation stage further increases the bit-width. To ensure hardware implementation efficiency, roundoff/quantization is necessary at the output port of the MAC unit. However, this approximation process often requires an additional computing block, leading to resource overhead.