Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/13553
Title: Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET
Authors: Nirala, Rohit Kumar
Semwal, Sandeep
Kranti, Abhinav
Keywords: 1T-DRAM;disturbance;energy;latency;nanowire;reconfigurable transistor (RFET);retention
Issue Date: 2024
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Nirala, R. K., Semwal, S., Gupta, M., & Kranti, A. (2024). Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET. IEEE Transactions on Electron Devices. Scopus. https://doi.org/10.1109/TED.2024.3371950
Abstract: The influence of the number of bias levels for realizing capacitorless dynamic random access memory (DRAM) in nanowire (NW) gate-all-around (GAA) reconfigurable transistor (RFET) is analyzed through simulations. Although a careful selection of bias levels can enhance retention (1.8 s at 85 0.C), reduce energy consumption (<inline-formula> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula>0.3 fJ), and enhance current ratio (CR) (<inline-formula> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula>10<inline-formula> <tex-math notation="LaTeX">$^{\text{5}}$</tex-math> </inline-formula>) in NW GAA RFET, bias-induced word line (WL) and bitline (BL) disturbance in an array can limit 1T-DRAM performance. It is shown that NW GAA RFET DRAM exhibits immunity from all six BL disturbances up to 5 ms while WL disturbance is critical as three out of six possible cases are disturbed. IEEE
URI: https://doi.org/10.1109/TED.2024.3371950
https://dspace.iiti.ac.in/handle/123456789/13553
ISSN: 0018-9383
Type of Material: Journal Article
Appears in Collections:Department of Electrical Engineering

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