Towards No Penalty Control Hazard Handling

Abstract

Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a novel mechanism that makes microcontrollers forgo branch predictors and thereby eliminate branch mispredictions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The proposed technique is implemented as five different modules that work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed system was tested using test-bench with modifications to make the test-code compatible with the designed architecture. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles. Moreover, the latency of instruction fetch stage of pipeline integrated with the proposed architecture is 330 ps (3 GHz approx.) which is more than the operating frequencies of microcontrollers. Therefore, the proposed design can be integrated in high performance microcontrollers. © 2023 IEEE.