Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics

Abstract

This paper presents a novel secure high-level synthesis (HLS) methodology for designing an optimized and secure reusable convolutional hardware accelerator against intellectual property (IP) piracy using retinal signature. These reusable hardware accelerator designs used in system-on-chips (SoCs) of computing systems are susceptible to the hardware threat of piracy. Therefore, the proposed approach firstly performs compiler driven high level transformation in order to optimize the design latency, followed by embedding the retinal biometric signature of IP vendor in the form of encoded hardware security constraints into structurally transformed scheduled design during register allocation module of HLS. These embedded security constraints thereby enable the robust detection against pirated design versions. The proposed approach achieves the following: i) optimized and secure design for convolutional hardware accelerator ii) robust detection against piracy at zero design cost overhead iii) significantly lower probability of coincidence (Px) indicating stronger digital evidence and higher tamper tolerance (TT) than recent approaches. © 2023 IEEE.