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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Semwal, Sandeep | en_US |
| dc.contributor.author | Rai, Nivedita | en_US |
| dc.contributor.author | Nirala, Rohit Kumar | en_US |
| dc.contributor.author | Kranti, Abhinav | en_US |
| dc.date.accessioned | 2024-07-18T13:48:28Z | - |
| dc.date.available | 2024-07-18T13:48:28Z | - |
| dc.date.issued | 2024 | - |
| dc.identifier.citation | Semwal, S., Rai, N., Nirala, R. K., Gupta, M., & Kranti, A. (2024). Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET. IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024. Scopus. https://doi.org/10.1109/EDTM58488.2024.10511949 | en_US |
| dc.identifier.isbn | 979-8350371529 | - |
| dc.identifier.other | EID(2-s2.0-85193284681) | - |
| dc.identifier.uri | https://doi.org/10.1109/EDTM58488.2024.10511949 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/14045 | - |
| dc.description.abstract | The interplay between quantum confinement (QC) and parameter variations in ultralow power (ULP) inverter and Schmitt trigger (ST) with nanowire junctionless transistor is evaluated. Process variations under QC lead to enhanced threshold voltage (V_TH) variability which degrades noise margin of ULP inverter. Similarly, QC induced higher VTH variation in n- or p-subcircuit degrades hysteresis width of ULP ST. Process variations under QC need to be carefully analyzed for optimum performance for ULP applications. © 2024 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024 | en_US |
| dc.subject | CMOS Inverter | en_US |
| dc.subject | Junctionless Transistor | en_US |
| dc.subject | Quantum confinement | en_US |
| dc.subject | Schmitt Trigger | en_US |
| dc.subject | Ultralow Power | en_US |
| dc.title | Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET | en_US |
| dc.type | Conference Paper | en_US |
| Appears in Collections: | Department of Electrical Engineering | |
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