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https://dspace.iiti.ac.in/handle/123456789/14910
| Title: | Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy |
| Authors: | Sengupta, Anirban |
| Keywords: | Convolutional layer;Encoded hash;Hardware security;HLS;IP design;Retina biometrics |
| Issue Date: | 2024 |
| Publisher: | Springer |
| Citation: | Chaurasia, R., & Sengupta, A. (2024). Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy. SN Computer Science. Scopus. https://doi.org/10.1007/s42979-024-03247-9 |
| Abstract: | The convolution layer in a convolutional neural network (CNN) is highly computationally intensive. It is crucial to design reusable low-cost hardware IP for convolutional layer for enabling hardware-based feature extraction. However, the involvement of fake IP vendor/untrustworthy broker in the integrated circuit (IC) supply chain, makes these IPs susceptible to the threat of piracy. The proposed approach presents high- level synthesis (HLS) driven watermarking methodology for designing low-cost and secure convolutional hardware IP. The presented watermarking approach employs complier-driven high-level transformation and exploits retinal signature fused with the encoded hash for piracy detective countermeasure. The proposed approach, therefore, firstly performs compiler-driven high-level transformation in order to optimize the design latency, followed by embedding the watermark of an authentic IP vendor. The generated watermark in the form of encoded hardware watermarking constraints (digital evidence) is covertly embedded into the resulting optimized design during the register allocation module of HLS. The proposed approach achieves the following: (i) optimized and secure design for convolutional hardware IP, (ii) robust detection of pirated IP at zero design cost overhead, (iii) significantly lower probability of coincidence (in the range of 1.3E−06 to 1.2E−09) indicating stronger digital evidence and higher tamper tolerance (in the range of 2.64E+460 to 9.60E+698) than recent approaches. © The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd. 2024. |
| URI: | https://doi.org/10.1007/s42979-024-03247-9 https://dspace.iiti.ac.in/handle/123456789/14910 |
| ISSN: | 2662-995X |
| Type of Material: | Journal Article |
| Appears in Collections: | Department of Computer Science and Engineering |
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