High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection

Abstract

High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation. All modern electronic gadgets have complex system-on-chips (SoCs) that rely heavily on data intensive application specific processors, for digital signal processing (DSP), machine learning, and image processing applications. These data-intensive cores, in the form of intellectual property (IP), form an integral part of various modern equipment and consumer applications, such as smart phones, smart watches, and tablets. High level synthesis (HLS) frameworks play a pivotal role in designing these application specific processors. However, the design of such processors can be exposed to several trust issues and hardware security threats, such as IP piracy, fraud IP ownership, and reverse engineering. Written by an expert author, this book is a source of information for readers on HLS solutions for hardware security. It covers topics such as HLS-based watermarking using retinal biometrics, HLS-based structural obfuscation, and detective countermeasure against HLS-based hardware Trojan attacks. This book is a useful resource for researchers, graduate students, and practising engineers working in electronics and chip design. © The Institution of Engineering and Technology and its licensors 2024.