HLS-based fingerprinting

Abstract

The utilization of hardware intellectual property (IP) cores within system-on-chip computing architectures offers a distinct advantage by enhancing design productivity while reducing the overall design cycle time. However, it is necessary to secure these IP designs against potential threats from the perspective of both, the seller and the buyer within the global design supply chain process. This chapter discusses an IP fingerprinting and symmetrical IP protection mechanism for securing IP buyer’s and IP seller’s rights. This chapter demonstrates the embedding of both a buyer’s fingerprint and a seller’s watermark simultaneously using the high-level synthesis (HLS) process. By integrating the buyer’s fingerprint and seller’s watermark into the IP design, robust protection against IP piracy/unauthorized usage and false IP ownership claim is ensured. © The Institution of Engineering and Technology and its licensors 2024.