HLS-based mathematical watermarks for hardware security and trust

Abstract

Ensuring security and trust within the global hardware design supply chain process is paramount. Intellectual property (IP) piracy and false IP ownership assertion are two primary threats that exist within the global design supply chain process. This chapter discusses a high-level synthesis (HLS)-based mathematical watermarking approach that exploits the characteristics of the design parameters and design space, viz. dispersion matrix and eigen decomposition framework, respectively. In this chapter, the IP seller is considered the defender and the system-on-chip (SoC) integration house is the attacker. The discussed mathematical watermarking methodology demonstrates a security framework that leverages the characteristics of the design space parameters chosen by the IP seller, as well as the design space’s size in terms of resource configurations selected by the IP seller, to embed them as unique features for safeguarding the IP design. The discussed approach also employs AES encryption to generate encrypted watermarking constraints, which are further integrated/embedded into the hardware design (serving as digital evidence) and provide detective security countermeasures against potential intellectual property piracy and false IP ownership claim. © The Institution of Engineering and Technology and its licensors 2024.