SRAM based in-memory computing architectures for AI hardware

Abstract

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decisionmaking AI applications stand out for their heavy reliance on data-centric operations, predominantly characterized by matrix and vector manipulations. Consequently, due to these computational patterns, conventional computer architectures that separate CPU and memory units (Von-Neumann model) face limitations in meeting AI’s performance and power requirements. The widespread application of deep learning (DL) in real-world scenarios, including computer vision, speech recognition, and robotics, has become increasingly pervasive. This application requires huge data, computing, and storage capacity. The escalating demand for computation and memory in DL workloads poses challenges across the entire spectrum of computing platforms, spanning from edge devices to the cloud. A critical bottleneck in current platforms is the “memory wall,” arising from the necessity to transfer huge amounts of data between memory and compute units, consuming significant time and energy resources. A promising solution to this challenge involves moving computations near/in memory. This approach is broadly known as “in-memory computing” (IMC). IMC has the potential to surmount the memory wall, significantly enhancing speed and reducing power consumption.