Resistive RAM based compute-in-memory architecture for content addressable memory

Abstract

The increasing demands of data-intensive applications necessitate high-speed, energy-efficient solutions that offer superior performance. Non-volatile memory devices, such as Resistive Random Access Memory (RRAM), have emerged as promising options for enhancing computing systems. In this thesis, we present an innovative 3T1R bitcell designed specifically for Binary Content Addressable Memory operations, implemented using 65nm CMOS technology. Our design achieves a 1.27x reduction in sensing latency and a 2.67x decrease in search energy consumption for a 64-bit word size compared to the current state-of-the-art. Additionally, the proposed bitcell demonstrates robust performance across various process corners and temperature variations, ensuring reliability in diverse operational environments. This thesis also introduces a novel approach for designing Ternary Content Addressable Memory bitcells using a Hybrid CMOS-RRAM (4T2R) configuration, enhancing the conventional 2T2R cell by adding extra comparison transistors. This enhancement addresses signal mismatch issues and effectively maintains the precharged value for the match signal. The proposed bitcell achieves significant improvements in latency and energy consumption over existing designs, with a latency of 0.35 ns for a 256-bit word size and an energy consumption of 0.81 fJ/bit/search. It surpasses existing designs in terms of the energy-delay product by an impressive 26.85%. These performance metrics, determined using 65 nm CMOS technology, highlight the bitcell’s versatility and effectiveness across various word sizes and applications. Overall, this work represents a significant advancement in TCAM design, offering enhanced speed and energy efficiency, which are critical for modern computing systems.