Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism

Abstract

The traditional Von Neumann architecture suffers from performance limitations due to its reliance on a shared bus/memory for data and instruction accesses. To reduce the dependence on shared bus, this paper explores the concept of in-memory computing with high-speed volatile memory for faster data processing. This study is specifically centered around crafting an area-efficient in-memory adder and sum-comparator within a 6-transistor Static Random Access Memory (SRAM) cell array. A variable reference voltage mechanism leveraging degraded switches connected in a transmission gate-based fashion is proposed. This mechanism, when applied to in-memory computations, can achieve multiple gate functionalities, which in turn significantly reduces the number of transistors required for the adder and sum-comparator. The design and Monte Carlo simulation were done in Cadence Virtuoso’s spectre simulator to validate the functionality and reliability of the proposed mechanism. Furthermore, the proposed design demonstrates comparable propagation delay with previous works while offering substantial reductions in area, which is quantified by 26% reduction in the number of transistors required and 36.5% reduction in static power dissipation. The integrated system of adder and sum-comparator implemented in a 128×64-bit SRAM array in 70 nm process technology exhibits promising performance metrics, with an access time of 0.471 ns at 2.18472 GHz, as simulated using an integrated Cache Access Time (CACTI) modeling tool. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.