Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications

Abstract

This paper introduces a novel methodology for designing secure hardware accelerator tailored for convolutional neural network (CNN) applications, leveraging security-aware high-level synthesis (HLS). The methodology outlined offers comprehensive security measures, including hindrance against reverse engineering (RE) and intellectual property (IP) piracy concerns through architectural transformations and embedded biometric palmprint constraints, respectively. Key contributions of this methodology include: i) robust hindrance against RE attack, ii) robust piracy detection with no additional design overhead, iii) definitive proof of IP ownership by achieving significantly lower probability of coincidence (P), indicating lower probability of false positive, and iv) enhanced tamper tolerance (TT) and resilience against brute force attacks compared to recent methodologies. © 2024 IEEE.