Alternative paradigms of hardware security for addressing threats of IP piracy and trojan during high level synthesis

Abstract

The use of hardware intellectual property (IP) cores has become a key design approach in modern electronics, particularly in electronics, computing, and multimedia systems. This popularity stems from the ability of IP cores to enhance performance and efficiency by accelerating application processes. In addition, growing design complexities, shorter product lifecycles, and increasing pressure to bring products to market faster (time-to-market factor) have driven the adoption of reusable IP cores in modern system-on-chip (SoC) designs. These factors, coupled with the data and computation intensive nature of many modern applications, have made IP cores an essential component in these designs. However, the growing reliance on third-party IP vendors and a globally distributed design supply chain has introduced significant security risks. As IP cores are often sourced from multiple vendors to expedite the design process, the involvement of external parties creates vulnerabilities that can be exploited by malicious actors. An untrusted design house, particularly in offshore locations, might steal or tamper with the IP core design, leading to piracy or malicious alterations, compromising the integrity and safety of the final product. On the other hand, it is also essential for the SoC integrator to demarcate between authentic and pirated products before integration into final SoC design to ensure the safety and security of end consumers.