Transient fault reliability and security of IP cores

Abstract

The rapid growth of consumer electronics (CE) industry has led to a cut-throat competition of developing sophisticated devices. As the complexity of the CE design increases along with shortening of time-to-market deadlines, the designers are becoming heavily reliant on reusable Intellectual Property (IP) cores generated at higher levels of design abstraction. A malicious attacker may exploit dependency on IP cores through security issues/vulnerabilities such as piracy, Trojan insertion, overbuilding, reverse engineering, etc. Hence, methodologies are required to ensure the security of the IP cores.Further similar to IP core security, IP core reliability is also becoming a major concern. As the demand for CE devices with sophisticated features such as low-power consumption, smaller silicon area, etc. increases, the IP core designers are heavily depending upon technology scaling to meet these design objectives. However, technology scaling enhances several reliability concerns such as bias temperature instability, multi-cycle, and multi-unit transient faults, electromigration, etc. Hence, methodologies are required for designing reliable IP cores.To advance the state-of-the-art for designing reliable and secured IP cores, this thesis makes following contributions: (a) A novel methodology for generating a DSP IP core that is simultaneously resilient/secure against multi-cycle (temporal) and (multi-unit) spatial effect of transient fault. (b) A novel methodology for generating a DSP IP core that is simultaneously tolerant against a multi-cycle temporal and multi-unit spatial effect of transient fault for data-intensive applications. (c) A novel methodology for generating a DSP IP core that is simultaneously tolerant against a multi-cycle temporal and multi-unit spatial effect of transient fault for loop-based control intensive applications. (d) A novel methodology for generating a low-cost, highly secure, functionally obfuscated DSP IP core. (e) A novel methodology for analyzing the aging effect of NBTI stress on the performance of DSP IP core. (f) A novel computational forensic engineering methodology for resolving ownership conflict of DSP IP core generated using high-level synthesis.