Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/17359
| Title: | Efficient in-memory computing architecture using SRAM |
| Authors: | Pandey, Akash |
| Supervisors: | Vishvakarma, Santosh Kumar |
| Keywords: | Electrical Engineering |
| Issue Date: | 19-May-2025 |
| Publisher: | Department of Electrical Engineering, IIT Indore |
| Series/Report no.: | MT362; |
| Abstract: | Compute-In-Memory (CIM) is a promising architectural paradigm that seeks to overcome the memory–compute bottleneck inherent in traditional von Neumann architectures. By integrating computation capabilities directly within the memory arrays, CIM enables localized data processing and significantly reduces energy and latency costs associated with frequent data movement between memory and processing units. This approach is particularly beneficial for data-intensive tasks such as neural network inference, where matrix-vector multiplication (VMM) is a dominant operation. Digital CIM architectures are favored for their accuracy, noise resilience, and compatibility with standard CMOS design flows, making them suitable for deployment in low-power edge AI systems. |
| URI: | https://dspace.iiti.ac.in:8080/jspui/handle/123456789/17359 |
| Type of Material: | Thesis_M.Tech |
| Appears in Collections: | Department of Electrical Engineering_ETD |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| MT_362_Akash_Pandey_2302102035.pdf | 5.97 MB | Adobe PDF | View/Open |
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